1. Field of the Invention
The present invention relates to a frequency determining apparatus. To be more specific, the present invention relates to an improvement of such a frequency determining apparatus that may be applicable to a multiple-system television receiver and may discriminate two different frame frequencies.
2. Description of the Prior Art
A multiple-system television receiver comprises such a frame frequency determining apparatus that discriminates between two television signals whose frame frequencies are different, such as 50 Hz and 60 Hz, for example, thereby to turn on a right vertical deflection circuit automatically. Such frame frequency determining circuits, in general, extract the vertical synchronizing pulses from the synchronizing signal, thereby to detect the period. Naturally, the periods of the vertical synchronizing pulses of 50 Hz and 60 Hz are 20 m sec and 16.7 m sec, respectively. In such cases where the synchronizing signal is disturbed by noises that have mixed in it when a television receiver is receiving a broadcast signal in the weak field intensity, or it is disturbed by reinsertion of a synchronizing signal when a video tape recorder is being played back in a special mode (such as speed search, stop mode), or the like, it becomes difficult to discriminate between the frame frequencies with the periods of 20 m sec and 16.7 m sec.
FIG. 1 is a block diagram showing an example of conventional frame frequency determining circuits. Referring to the drawing, vertical synchronizing pulses from the vertical synchronizing pulse separator circuit 1 are applied to a monostable multivibrator 3. Horizontal synchronizing pulses from a horizontal oscillator circuit 2 are given to a binary counter 4. The monostable multivibrator 3 is adapted so that it converts the received vertical synchronizing pulses into the pulses delayed by 6 m sec. The output 10 (the signal to be determined) from the monostable multivibrator 3 is given to the binary counter 4. The binary counter 4 includes a 1/64 frequency divider 41 and a 1/2 frequency divider 42. The signal to be determined 10 is provided for each of the 1/64 frequency divider and the 1/2 frequency divider as a clear signal. In the mean time, the horizontal synchronizing pulses that are inputted to the binary counter 4 are given to the 1/64 frequency divider 41 and undergo the frequency determination thereby. The output from the 1/64 frequency divider 41 is given to the 1/2 frequency divider and is also given to one input of a NAND gate 5 as the ouput Q7. The output from the 1/2 frequency divider 42 is given to the other input of the NAND gate 5 as the output Q8. The output from the NAND gate 5 is given through an integrator circuit 6 and an inverter 7 to a data input (D) of a D-type flip-flop 8. The signal to be determined 10 from the monostable multivibrator 3 is given to a clock input (CK) of the D-type flip-flop 8, wherein, since both the preset terminal (PR) and the clear terminal (CL) are grounded, the D-type flip-flop 8 functions so that, when its input D is at the high level, its output Q will reach the high level at the rise of the input CK. This output Q is taken out as the determined signal 9.
FIG. 2 is a time chart explaining the operation of the circuit shown in FIG. 1 in determining the frequency of the vertical synchronizing pulses when it is free from noise. With reference to FIG. 2, a description will be made in the following of the normal operation taking place in the case where the vertical synchronizing pulses are free from noise. In the case where the frequency of the vertical synchronizing pulses shown in FIG. 2 (a) is 50 Hz, the period of the signal to be determined 10 is 20 m sec. The 1/64 frequency divider 41 and the 1/2 frequency divider 42 are enabled from the point of the fall of the signal to be determined 10. The frequency of the output Q7 from the 1/64 frequency divider 41 shown in FIG. 2 (b) will become a 1/64 frequency division of the frequency of the horizontal synchronizing pulses, 15.625 kHz. Hence, the output Q7 from the 1/64 frequency divider becomes such pulses of 244 Hz that will rise after 4.096 m sec (64 H) and will fall after further 4.096 m sec. The output Q8 from the 1/2 frequency divider 42 shown in FIG. 2 (c) will, similarly due to the frequency division of 1/64.times.1/2=1/128, rise 8.19 m sec, and fall 16.38 m sec, after the point of the fall of the signal to be determined 10. Practically, however, since the clearing input of the signal to be determined 10 enters before that, the output Q8 from the 1/2 frequency divider falls simultaneously with the rise of the signal to be determined 10. The output of the NAND gate becomes low when both the outputs Q7 and Q8 are of the high level (FIG. 2 (d)). This output from the NAND gate 5 is, after being delayed by a time .tau.d by means of the integrator circuit 6, inverted by the inverter 7. As described above, the D-type flip-flop 8 functions so that, when its input D is of the high level, its output Q becomes the high level at the rise of the input CK. As shown in FIG. 2 (e) and (f), in the case where the frame frequency is 50 Hz, the signal to be determined 10, namely the input CK of the D-type flip-flop 8, rises while the input D of the flip-flop 8 is at the high level and, therefore, the output Q of the flip-flop 8 is always at the high level. Hence the determined signal 9 is always the high level.
In the following a description will be made of the case where the frame frequency is 60 Hz, namely the period of the signal to be determined 10 is 16.7 m sec (FIG. 2 (g)). While the signal Q7 will, as shown in FIG. 2 (h), behave similarly to the above case, the signal Q8 will, as shown in FIG. 2 (i), fall to the low level, at the rise of the signal to be determined 10, before the Q7 rises to the next high level, and thus the output of the NAND gate 5, or Q7.Q8, is always held at the high level. Accordingly, in this case, the input D (not shown in the drawing) of the D-type flip-flop 8 always becomes the low level. In the D-type flip-flop 8 whose input D is thus held at the low level, its output Q becomes the low level at the rise of the input CK and the output Q thereafter keeps on this state.
As described thus far, the determined output 9 becomes the high level when the frame frequency is 50 Hz and becomes the low level when the same is 60 Hz and thus the circuit shown in FIG. 1 is understood to have the desired determining function.
However, the circuit shown in FIG. 1 is apt to malfunction when receiving the signal at 50 Hz, whereas it is unlikely to do so when receiving the signal at 60 Hz. This will be explained below.
FIG. 3 is a time chart for explaining a probable malfunction of the circuit shown in FIG. 1 when receiving the signal at 50 Hz. On the occasion when vertical synchronizing pulses free from mixed-in noises are outputted from the vertical synchronizing pulse separator circuit 1, the output from the monostable multivibrator 3, namely the signal to be determined 10, will, as shown in FIG. 3 (b) be such pulses each of which may fall 6 m sec after its rise as described above. Now assume a case where the vertical synchronizing pulses with mixed-in noises n1, n2, and n3 as shown in FIG. 3 (c) are outputted from the vertical synchronizing pulse separator circuit 1. At that time, the monostable multivibrator 3 is not affected at all by the noise nl which falls within the delay time 0 - S1 (FIG. 3 (d)) of the monostable multivibrator 3, but it is affected by the noise n2 which is mixed in after the end of the delay time S1 and produces a pulse lasting from 6 m sec from the point of the rise of the noise n2. Since the binary counter 4 is enabled after the delay time has passed, namely from the point S1, if there is no noise mixed in, the signals Q7, Q8, and Q7.Q8 (the logical product of Q7 and Q8) behave properly as shown in FIG. 3 (e), (f), and (g), respectively, but if there is such a noise as the noise n2, the binary counter 4 starts to operate again from the point S2, and thus the signals Q7, Q8, and Q7.Q8 behave as shown in FIG. 3 (h), (i), and (j), and hence the input D of the D-type flip-flop does not appear. Therefore, the range of time of the occurrence of a malfunction in the construction as shown in FIG. 1 when receiving the signal at 50 Hz is 192H from the point 6 m sec after the rise of the normal vertical pulse as indicated in FIG. 3 (k). To be more specific, a malfunction will occur if a noise gets mixed in within the range of time.
FIG. 4 is a time chart showing the operation of the circuit as shown in FIG. 1 when determining the vertical synchronizing signal at 60 Hz. As explained in the foregoing with reference to FIGS. 1 and 2, since the signal Q8 becomes the low level at the rise of the signal to be determined 10 before the signal Q7 becomes the high level, even if there are such noises mixed in as n1, n2, and n3 that are mentioned in the above explanation with reference to FIG. 3, a malfunction will not occur. To be more specific, even if the noise n2 gets mixed in after the end (S1) of the delay time causing the binary counter 4 to operate again, there is no possibility for both the singals Q7 and Q8 to become the high level simultaneously and, therefore, Q7.Q8 is kept on at the high level and the signal at the low level is outputted from the D-type flip-flop 8.
FIG. 5 is a block diagram showing another example of conventional frame frequency determining circuits. In the circuit in FIG. 5, the output Q7 from the 1/64 frequency divider 41 is applied to the NAND gate 5 through the inverter 11. Hence the NAND gate 5 will output the signal Q7.Q8 and the output Q is taken out from the D-type flip-flop 8 as the determined output 9.
FIG. 6 is a flow chart explaining a normal operation of the circuit in FIG. 5. A description of a normal operation in the circuit in FIG. 5 will be given below with reference to FIG. 6.
First considering a case where the signal to be determined 10 is 60 Hz, the similar operation to the case previously described with reference to FIG. 2 will take place, but when the input D of the D-type flip-flop 8 is the high level, namely when the signal obtained by means of the delaying by a time .tau.d and the inversion by the inverter 7 of the signal Q7.Q8 is the high level as indicated in FIG. 6 (e), the rise of the input CK at that time will cause the output Q to become the high level as shown in FIG. 6 (f), hence the output Q becomes the low level. Thus, this output Q, namely the determined signal 9, is held at the low level.
Then, considering a case with 50 Hz, as indicated in FIG. 6 (j), when the input D is the low level, the input CK will rise, and therefore the output Q will become the low level and the output Q will become the high level (not shown in the drawing).
As explained thus far, the circuit in FIG. 5 provides quite the same results to the determined output 9 as does the circuit in FIG. 1. As will be explained below, however, the circuit in FIG. 5, contrary to the circuit in FIG. 1, is apt to malfunction when receiving the signal at 60 Hz, but is unlikely to make such a malfunction when receiving the signal at 50 Hz.
FIG. 7 is a time chart explaining the occurrence of a malfunction in the circuit in FIG. 5 when receiving the signal of 50 Hz. FIG. 8 is a time chart explaining the occurrence of a malfunction when receiving the signal at 60 Hz.
Referring to FIG. 7, the state of the circuit in which a malfunction occurs when it is receiving the signal of 50 Hz is similar to that described above with reference to FIG. 3 and, although a detailed explanation is omitted here, it would be appreciated that a malfunction occurs if noise gets mixed in during the period of time when the signal Q7.Q8 is the high level in the course of the normal operation, because this period of time corresponds to the time for a normal pulse to arise for the signal at 50 Hz.
As to the malfunction in the circuit in FIG. 5 when receiving the signal at 60 Hz, the range of time for the occurrence of the malfunction it is the period of 128H as indicated in FIG. 8.
As explained thus far, it would be appreciated that the frequency determining circuit in FIG. 5, contrary to the frequency determining circuit in FIG. 1, is apt to malfunction when receiving the signal at 60 Hz and less liable to cause such a malfunction for the signal of 50 Hz. Therefore either the frequency determining circuit mentioned with reference to FIG. 1 or that with reference to FIG. 5 has both merits and demerits, and thus the accurate frequency determination has not been possible so far.